As is well known, solid state storage devices such as SD cards or solid state storage drives (SSD) are widely used in a variety of electronic devices. Generally, a solid state storage device comprises a controlling circuit and a non-volatile memory.
Moreover, a NAND-based flash memory is one kind of non-volatile memory. Depending on the amount of data to be stored, the NAND-based flash memories may be classified into three types, i.e. a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory and a triple-level cell (TLC) flash memory. The SLC flash memory can store only one bit of data per cell. The MLC flash memory can store two bits of data per cell. The TLC flash memory can store three bits of data per cell.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 is connected with a host 14 through an external bus 12. Generally, the external bus 12 is a USB bus, an SATA bus, a PCIe bus, or the like. Moreover, the solid state storage device 10 comprises a controlling circuit 101 and a non-volatile memory 105. The controlling circuit 101 is connected with the non-volatile memory 105 through an internal bus 107. According to a command from the host 14, the controlling circuit 101 stores the received write data into the non-volatile memory 105, or the controlling circuit 101 acquires a read data from the non-volatile memory 105 and transmits the read data to the host 14.
The controlling circuit 101 further comprises an error correction (ECC) unit 104 and a retry table 106. The ECC unit 104 is used for correcting the error bits of the read data. After the error bits of the read data are corrected, corrected read data are transmitted to the host 14. However, if the ECC unit 104 is unable to successfully correct all bits of the read data, the read data cannot output the read data to the host 14. Under this circumstance, the retry table 106 provides another read voltage to the controlling circuit 101. According to the read voltage, the controlling unit 101 performs a read retry operation on the non-volatile memory 105.
FIG. 2A schematically illustrates the architecture of cells in the non-volatile memory of the solid state storage device. The non-volatile memory 105 has a memory array composed of plural cells. Each cell includes a floating gate transistor. The memory array comprises plural word lines WL(n−1), WL(n) and WL(n+1) for controlling respective rows of cells. When one of the plural word lines is activated, a selected row corresponding to the activated word line is determined. According to the on/off states of the floating gate transistors of the cells in the selected row, the storing states of the cells are determined. Moreover, the cells are SLC, MLC or TLC cells.
Generally, the floating gate transistor of each cell has a floating gate to store hot carriers. A threshold voltage (VTH) of the floating gate transistor is determined according to the amount of the stored hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the solid state storage device, the amount of hot carriers to be injected into the floating gate is controlled by the controlling circuit 101, so that the threshold voltage (VTH) of floating gate transistor is correspondingly changed. During a read cycle, the controlling circuit 101 provides a read voltage to the floating gate of the floating gate transistor and determines the storing state of the floating gate transistor by judging whether the floating gate transistor is turned on.
FIG. 2B schematically illustrates the threshold voltage distribution curves of the MLC flash memory in different storing states. Each cell of the MLC flash memory can be programed into one of four storing states E, A, B and C according to the amount of the injected hot carriers. Before the hot carriers are injected into the cell, the cell is in a storing state E. According to the number of hot carriers injected into the cell, the cell is in the storing state A, the storing state B or the storing state C. The cell in the storing state C has the highest threshold voltage. The cell in the storing state E has the lowest threshold voltage. After an erase cycle, the cell is returned to the storing state E where no hot carriers are injected into the cell.
Moreover, each cell of the SLC flash memory has two storing states, and each cell of the TLC flash memory has eight storing states. Hereinafter, only the cells of the MLC flash memory will be described. It is noted that the concepts of the present invention are also applied to the SLC flash memory and the TLC flash memory.
In practical, even if many cells are in the same storing state during the program cycle, the threshold voltages of these cells are not all identical. That is, the threshold voltages of these cells are distributed in a specified distribution curve with a median threshold voltage. As shown in FIG. 2B, the cells in the storing state E have a median threshold voltage VTHE (e.g. 0V), the cells in the storing state A have a median threshold voltage VTHA (e.g. 10V), the cells in the storing state B have a median threshold voltage VTHB (e.g. 20V), and the cells in the storing state C have a median threshold voltage VTHC (e.g. 30V). In other words, a greater number of the cells in the storing state A have the median threshold voltage VTHA (e.g. 10V).
Please refer to FIG. 2B again. According to the above characteristics of the MLC flash memory, a read voltage set including three read voltages Vra, Vrb and Vrc is defined. During the read cycle, the controlling circuit 101 provides the three read voltages of the read voltage set to the word line in order to detect the storing states of the cells of the MLC flash memory.
For example, when the read voltage Vrb is provided to the non-volatile memory 105, a most significant bit (MSB) of the cell can be determined. If the threshold voltage of the cell is lower than the read voltage Vrb and the cell can be turned, the controlling circuit 101 judges that the MSB of the cell is “1”. Whereas, if the threshold voltage of the cell is higher than the read voltage Vrb and the cell cannot be turned, the controlling circuit 101 judges that the MSB of the cell is “0”. Similarly, after the read voltage Vra and the read voltage Vrc are provided to the non-volatile memory 105, a least significant bit (LSB) of the cell can be determined. Consequently, the storing state E is denoted as a logic state is “11”, the storing state A is denoted as a logic state “10”, the storing state B is denoted as the logic state “00”, and the storing state C is denoted as the logic state “01”.
Similarly, the controlling circuit 101 can employ one read voltage to determine two storing states of the SLC flash memory. Similarly, the controlling circuit 101 can use a read voltage set including seven read voltages to determine eight storing states of the TLC flash memory.
As mentioned above, the read voltages Vra, Vrb and Vrc are important for determining the storing states of the cells. However, after the non-volatile memory 105 has been used for a certain time period, the characteristics of the cells are subjected to changes. Under this circumstance, the threshold voltage distribution curves of the storing state of all cells in the non-volatile memory 105 are possibly changed, and the median threshold voltages are shifted. If the original read voltages Vra, Vrb and Vrc are still used to read the data of the non-volatile memory 105, the number of error bits increases. Since the number of the erroneously-judged cells increases, the ECC unit 104 cannot effectively correct the erroneously-judged cells. Under this circumstance, the controlling circuit 101 cannot output the corrected read data to the host 14.
For solving the above drawbacks, the controlling circuit 101 has a retry table. For example, the retry table contains plural read voltage sets stored in a memory. If the controlling circuit 101 confirms that a read retry operation is required, the controlling circuit 101 acquires another read voltage set including three read voltages Vra′, Vrb′ and Vrc′ from the retry table 106. Moreover, the read voltages Vra′, Vrb′ and Vrc′ are provided to the non-volatile memory 105 in order to read the data again.
FIG. 2C is a flowchart illustrating a decoding process of the conventional solid state storage device. Firstly, the controlling circuit 101 provides a default read voltage set including read voltages Vra, Vrb and Vrc to the non-volatile memory 105 in order to read data from the non-volatile memory 105 (Step S302). Then, the controlling circuit 101 judges whether the data is successfully decoded (Step S304).
If the data is successfully decoded by the ECC unit 104 in the Step S304, it means the error bits in the read data can be corrected. Consequently, the controlling circuit 101 outputs the read data (Step S310). Whereas, if the data is not successfully decoded in the Step S304, it means that the error bits in the read data cannot be effectively corrected. Consequently, the controlling circuit 101 performs a read retry process (Step S305).
In the read retry process Step S305, the controlling circuit 101 acquires an updated read voltage set including read voltages Vra′, Vrb′ and Vrc′ from the retry table 106, and provides the updated read voltage set to the non-volatile memory 105 in order to read data from the non-volatile memory 105 (Step S306). Then, the controlling circuit 101 judges whether the data can be successfully decoded (Step S308).
For example, M read voltage sets have been previously listed and contained in the retry table 106. During the read retry process S305, the M read voltage sets are sequentially used as the updated read voltage sets and provided to the non-volatile memory 105. According to the updated read voltage sets, the controlling circuit 101 reads the data from the non-volatile memory 105 again. If the data is successfully decoded according to the updated read voltage sets, the controlling circuit 101 outputs the read data (Step S310) and ends the read retry process S305. Whereas, if the data is not successfully decoded according to all of the M read voltage sets, it means that the read retry process fails. Under this circumstance, the controlling circuit 101 generates a failed message to indicate that the read retry process fails (Step S312). In other words, the steps S306 and S308 are performed M times at most during the read retry process.
From the above discussions, if the data is successfully decoded according to the default read voltage set, the controlling circuit 101 will not perform the read retry process. Under this circumstance, all of the M read voltage sets in the retry table 106 are not used. On the other hand, if the controlling circuit 101 performs the read retry process, the M read voltage sets in the retry table 106 are possibly used.
Moreover, the M read voltage sets in the retry table 106 are provided by the manufacturer of the non-volatile memory 105. During the read retry process, the controlling circuit 101 sequentially reads the M read voltage sets from the retry table 106 and sequentially provides the M read voltage sets to the non-volatile memory 105. Since the read retry process is only able to sequentially provide the M read voltage sets to the non-volatile memory 105 but is unable to directly acquire the suitable read voltage set, the read retry process is time-consuming.